Non-volatile memory device formed with etch stop layer in shallow trench isolation region

ABSTRACT

A method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate.

BACKGROUND

This disclosure relates generally to the field of computer memory, andmore particular to a non-volatile memory (NVM) device formed with anetch stop layer in the shallow trench isolation (STI) regions.

NVM devices are used in various types of computer memory, for example,flash devices. An NVM device includes a floating gate separated from acontrol gate by a gate dielectric layer. A major concern in NVM devicesis the gate coupling factor. A high gate coupling factor results in goodcontrol of the floating gate by the control gate during device operationand increases NVM device performance. The gate coupling factor of a NVMdevice is dependent on both the capacitance between the control gate andthe floating gate, and the capacitance between the floating gate and thesubstrate. For an increase of 1 volt (V) of the control gate potential,the floating gate potential increases by a factor α_(CG), which is afactor related to the coupling factor between the floating gate and thecontrol gate. α_(CG) needs to be relatively low to ensure good controlof the floating gate by the control gate during device operation.However, capacitance that exists between the floating gate and thedevice substrate may act to raise α_(CG). Therefore, in order to raisethe gate coupling factor of a NVM device, the capacitance between thecontrol gate and the floating gate needs to be raised and/or thecapacitance between the substrate and the floating gate needs to belowered.

One way to increase the capacitance between the floating gate and thecontrol gate is to decrease the equivalent oxide thickness (EOT) of thegate dielectric located between the floating gate and control gate.However, if the gate dielectric is made too thin, a tunneling currentbetween the floating gate and control gate may arise, leading to theloss of data that is stored in the NVM device. Various floating gateshapes that are used in NVM devices to increase the capacitance betweenthe floating gate and the control gate may also have the effect ofincreasing the capacitance between the floating gate and the substrate,which results in a relatively low net increase in the gate couplingfactor of the device, and hence low increase in NVM device performance.

BRIEF SUMMARY

In one aspect, a method includes forming a shallow trench isolation(STI) region in a substrate, the STI region comprising an etch stoplayer; etching the STI region by a first etch to the etch stop layer toform a recess in the STI region; and forming a floating gate, thefloating gate comprising a portion that extends into the recess in theSTI region, wherein the etch stop layer separates the portion of thefloating gate that extends into the recess in the STI region from thesubstrate.

In another aspect, a device includes a substrate; a shallow trenchisolation (STI) region located in the substrate, the STI regioncomprising an etch stop layer, and further comprising a recess in theSTI region, the recess having a bottom and sides, wherein the sides ofthe recess are defined by the etch stop layer; and a floating gate,wherein a portion of the floating gate is located on a side of therecess in the STI region and is separated from the substrate by the etchstop layer.

Additional features are realized through the techniques of the presentexemplary embodiment. Other embodiments are described in detail hereinand are considered a part of what is claimed. For a better understandingof the features of the exemplary embodiment, refer to the descriptionand to the drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Referring now to the drawings wherein like elements are numbered alikein the several FIGURES:

FIG. 1 illustrates a flowchart of an embodiment of a method of forming aNVM device formed with an etch stop layer in a STI region.

FIGS. 2A-B illustrate flowcharts of embodiments of methods of forming ashallow trench isolation (STI) region with an etch stop layer for a NVMdevice.

FIG. 3 is a cross sectional view illustrating an embodiment of asubstrate after formation of a padox layer over the substrate.

FIG. 4 is a cross sectional view illustrating an embodiment of a deviceafter formation of a nitride layer over the oxide layer.

FIG. 5 is a cross sectional view illustrating an embodiment of a deviceafter patterning the nitride layer and the oxide layer.

FIG. 6 is a cross sectional view illustrating an embodiment of a deviceafter formation of a STI trench.

FIG. 7 is a cross sectional view illustrating an embodiment of a deviceafter formation of a STI liner in the STI trench.

FIG. 8 is a cross sectional view illustrating an embodiment of a deviceafter formation of an etch stop layer over the STI liner.

FIG. 9 is a cross sectional view illustrating an embodiment of a deviceafter formation of a STI oxide fill.

FIG. 10 is a cross sectional view illustrating an embodiment of a deviceafter chemical mechanical polishing of the STI oxide fill and removal ofthe patterned padox and nitride.

FIG. 11 is a cross sectional view illustrating an embodiment a deviceafter etching the STI oxide fill down to the etch stop layer.

FIG. 12 is a cross sectional view illustrating an embodiment of a deviceafter well implantation and tunnel oxide growth.

FIGS. 13A-B are cross sectional views illustrating embodiments of adevice after formation of floating gates.

FIG. 14 is cross sectional view illustrating an embodiment of a deviceafter formation of a gate dielectric layer.

FIG. 15 is a cross sectional view illustrating an embodiment of a deviceafter formation of a control gate.

FIG. 16 is a cross sectional view illustrating an embodiment of a deviceafter etching a portion of the etch stop layer located at the bottom ofthe STI trench.

FIG. 17 is a cross sectional view illustrating an embodiment of a deviceafter formation of a STI oxide fill.

FIG. 18 is a cross sectional view illustrating an embodiment of a deviceafter chemical mechanical polishing of the oxide fill and removal of thepatterned padox and nitride.

FIG. 19 is a cross sectional view illustrating an embodiment of a deviceafter etching a portion of the STI oxide fill to the etch stop layer.

FIG. 20 is a cross sectional view illustrating an embodiment of a deviceafter well implantation and tunnel oxide growth.

FIGS. 21A-B are cross sectional views illustrating embodiments of adevice after formation of floating gates.

FIG. 22 is a schematic block diagram of a cross sectional viewillustrating an embodiment of a device after formation of a gatedielectric layer.

FIG. 23 is a schematic block diagram of a cross sectional viewillustrating an embodiment of a device after formation of a controlgate.

DETAILED DESCRIPTION

Embodiments of a NVM device formed with an etch stop layer in a shallowtrench isolation (STI) region, and a method of forming a NVM device withan etch stop layer in a STI region are provided, with exemplaryembodiments being discussed below in detail. Inclusion of an etch stoplayer in the STI region allows controlled etching of a recess in the STIregion. The floating gate and the control gate of the NVM device arethen formed such that they extend into the recess in the STI region,inducing a relatively high capacitance between the floating gate and thecontrol gate. The floating gate may be separated from the substrate bythe etch stop layer, so that the distance between the floating gate andsubstrate may be relatively high, resulting in a relatively lowcapacitance between the substrate and the floating gate. The overallcoupling factor of the device may be thereby increased. The etch stoplayer may be located on the both the sides and bottom of the STI trenchin some embodiments, or may only be located on the sides of the STItrench in other embodiments. Inclusion of etch stop layers in the STIregions between NVM devices may also reduce variability in the gatecoupling factor across a plurality of NVM devices.

FIG. 1 shows a flowchart of a method 100 of forming a NVM device with anetch stop layer in a shallow trench isolation (STI) region. Twoembodiments of the process flow of FIG. 1 are discussed in detail. Inthe first embodiment, the etch stop layer in the STI region may beformed such that the etch stop layer covers the sides and bottom of theSTI trench; formation of a STI region including such an etch stop layerin the STI region is discussed with respect to method 200A of FIG. 2A,and the process flow of formation of a memory device according to thefirst embodiment is discussed with respect to FIGS. 3-15. In the secondembodiment, the etch stop layer in the STI region may be formed suchthat the etch stop layer only covers the sides of the STI trench;formation of a STI region including such an etch stop layer in the STIregion is discussed with respect to method 200B of FIG. 2B, and theprocess flow of formation of a memory device according to the firstembodiment is discussed with respect to FIGS. 3-8 and 16-23.

Turning to the first embodiment of the process flow of method 100 ofFIG. 1, first, in block 101 of FIG. 1, STI regions comprising an etchstop layer may be formed in a wafer comprising a silicon substrate. Aflowchart of a method 200A of formation of the STI regions according tothe first embodiment is shown in FIG. 2A. Referring to FIG. 2A, in block201A, first, a padox layer, which comprises a uniform, relatively thinlayer of oxide, may be formed on a top surface of a silicon substrate.FIG. 3 shows an embodiment of a device 300 including a silicon substrate301 after formation of a padox layer 302 on the top surface of thesilicon substrate. Then, returning to FIG. 2A, flow proceeds to block202A, in which a nitride layer may be formed over the padox layer.

FIG. 4 shows the device 300 of FIG. 3 after formation of a nitride 401over the padox layer 302.

Next, returning to method 200A of FIG. 2A, in block 203A the nitride andthe padox are etched to form a mask for etching of an STI trench. Thepadox acts as an etch stop for the nitride during patterning of thenitride; the padox may then be subsequently patterned. FIG. 5 shows thedevice 400 of FIG. 4 after etching the nitride 401 and the padox layer302. Then, proceeding to block 204A of method 200A of FIG. 2A, the STItrench may be etched in the silicon substrate. FIG. 6 shows the device500 of FIG. 5 after etching of an STI trench 601 in the siliconsubstrate 301. After etching of the STI trench, flow of method 200A ofFIG. 2A proceeds to block 205A, in which an STI liner may be formed inthe STI trenches. The STI liner may comprise oxide, and may be formed byany appropriate method. FIG. 7 shows the device 600 of FIG. 6 afterformation of an STI liner 701 on the bottom and sides of the STI trench601.

Flow of method 200A of FIG. 2A then proceeds to block 206A, in which theetch stop layer may be deposited over the STI liner in the STI trench.The etch stop layer may comprise nitride. FIG. 8 shows an embodiment ofthe device 700 of FIG. 6 after deposition of the etch stop layer 801over the STI liner 701. The etch stop layer covers the bottom and sidesof the STI trench 601. The thickness of the etch stop layer determinesthe distance between the floating gate (discussed below with respect toblock 104) and the substrate; therefore the deposition of the etch stoplayer may be controlled to produce an etch stop layer having a desiredthickness to improve the operation of the finished NVM device. Method200A of FIG. 2A then proceeds to block 207A, in which an STI oxide fillmay be deposited over the device, filling STI trench over the etch stoplayer. FIG. 9 shows the device 800 of FIG. 8 after deposition of theoxide fill 901 over the device 800; the oxide fill 901 fills the STItrench 601 and covers the etch stop layer 801. Lastly, in block 208A ofFIG. 2A, the top of the STI oxide fill may be polished down to exposethe top surface of the etch stop layer, the excess etch stop and nitrideon top of the substrate are removed by etching, the padox may be removedby etching so as to expose the top surface of the silicon substrate, andthe top of oxide fill may be further removed to the level of the topsurface of the silicon substrate. The excess oxide fill may be removedby chemical mechanical polishing (CMP) in some embodiments. FIG. 10shows the device 900 of FIG. 9 after removal of the excess portion ofoxide fill 901, the excess portion of the etch stop layer 801, nitride401, and padox layer 302 to expose the top surface of silicon substrate301. Device 1000 of FIG. 10 comprises a silicon substrate 301 with STIregions including STI liner 701, etch stop layer 801 over the STI liner701, and STI oxide fill 1001.

Returning to method 100 of FIG. 1, after formation of STI regionsincluding an etch stop layer on the sides and bottom of the STI trenchaccording to the method 200A outlined in FIG. 2A in block 101 of FIG. 1,flow proceeds to block 102, in which the oxide fill in the STI regionsmay be etched to form a recess. In the first embodiment of the processflow of FIG. 1, the oxide fill may be etched down to the etch stop layeron the sides and the bottom of the STI trench. The etch of the oxidefill may comprise a hydrofluoric (HF) etch in some embodiments. FIG. 11shows the device 1000 of FIG. 10 after etching the oxide fill 1001 downto etch stop layer 801 to form recess 1101.

Flow of method 100 of FIG. 1 then proceeds to block 103, in which wellimplantation and tunnel oxide growth may be performed. The wellimplantation forms active regions in the silicon substrate near the topsurface of the substrate. In some embodiments, the well implantation maybe performed before etching of the STI oxide fill may be performed inblock 102 of FIG. 1. After well implantation, tunnel oxide may be grownover the implanted well regions of the substrate. The well regionimplantation and the tunnel oxide growth may be performed by anyappropriate method. For example, the tunnel oxide may be grown bychemical vapor deposition (CVD) or in-situ steam generation (ISSG) invarious embodiments. The tunnel oxide may comprise a high k dielectricsuch as hafnium oxide (HfO₂), hafnium silicate (HfSiO₂) nitrided hafniumsilicate (HfSiON), silicon oxinitride (SiO_(x)N_(y)), silicon nitride(Si₃N₄) or aluminum oxide (Al₂O₃) in some embodiments. In someembodiments, the order of blocks 102 and 103 in method 100 of FIG. 1 maybe reversed, and the etch of the oxide fill that is performed in block102 may be performed after the well implantation and tunnel oxide growthof block 103. FIG. 12 shows the device 1100 of FIG. 11 afterimplantation of well regions 1202 in the silicon substrate 301, andafter growth of tunnel oxide 1201 over the well regions 1202.

Turning again to method 100 of FIG. 1, in block 104, the floating gatesmay be formed by deposition and patterning of a floating gate material,which may comprise polysilicon or a metal such as titanium nitride(TiN), titanium aluminum nitride (TiAlN), and tantalum nitride (TaN), ormay comprise multiple layers, such as a polysilicon layer on top of oneor more metal layers. The floating gates may be deposited by conformaldeposition, and are formed such that a portion of the floating gates maybe located on the etch stop layer in the STI recess that was formed byremoval of the oxide fill from the STI regions. In various embodiments,the sides of the floating gates may be vertical, or in other embodimentsthe sides of the floating gates may be sloped. In embodiments in whichthe sides of the floating gates are sloped, the etch chemistry of theetch that is used to pattern a polysilicon floating gate may beCH_(x)F_(y)+O₂, and the angle of the slope may be about 10 degrees. Inother embodiments, the etch chemistry used to pattern a polysiliconfloating gate may be HBr+O or HCl+O. Floating gates with sloped sidesmay help to prevent formation of voids during deposition of the controlgate (discussed below with respect to block 106 and FIG. 15).Additionally, in some embodiments, the sides of the floating gateregions may be implanted with dopants after deposition. The implantationmay comprise tilted implantation in some embodiments. FIGS. 13A-B showthe device 1200 of FIG. 12 after formation of floating gates 1301A,1302A, 1301B, and 1302B. Floating gates 1301A and 1302A as shown in FIG.13A have vertical sides extending into recess 1101, and floating gates1301B and 1302 b as shown in FIG. 13B has sloped sides extending intorecess 1101. The depth and shape of the floating gates 1301A, 1302A,1301B, and 1302B may be dependent on the etch chemistry used to patternthe floating gate material after it is deposited; a floating gate suchas floating gates 1301A, 1302A, 1301B, and 1302B may have anyappropriate depth and shape in various embodiments. Additionally, whileFIGS. 14-15, which illustrate further processing steps of method 100 ofFIG. 1, are shown with respect to an example device 1300A includingfloating gates 1301A and 1302A with vertical sides, the same processingsteps may be applied to the device 1300B including floating gates 1301Band 1302B with sloped sides to form a memory device in variousembodiments. A NVM that includes floating gates such as floating gates1301A-B having sloped sides may help to prevent void formation duringdeposition of the control gate. Each of floating gates 1301A, 1302A,1301B, and 1302B comprise a portion that is located in the STI recess1101 on the etch stop layer 801, which separates the floating gates1301A, 1302A, 1301B, and 1302B from the substrate 301, lowering thecapacitance between the floating gates 1301A, 1302A, 1301B, and 1302Band the substrate 301.

Returning to method 100 of FIG. 1, in block 105, a gate dielectric layermay be deposited over the device, covering the floating gates and theetch stop layer located at the bottom of the recess. The gate dielectriclayer may be formed by conformal deposition, and may include one or morelayers of oxide and/or nitride. The gate dielectric layer may comprise ahigh k dielectric such as HfO₂, HfSiO₂, HfSiON, SiO_(x)N_(y) or Al₂O₃ insome embodiments. Additionally, in some embodiments, the gate dielectriclayer may include an oxide-nitride-oxide (ONO) dielectric layer. FIG. 14shows the device 1300A of FIG. 13A after formation of the gatedielectric layer 1401 over the floating gates 1301A and 1302A and theportion of the etch stop layer 801 that is located at the bottom ofrecess 1101.

Lastly, the flow of method 100 of FIG. 1 proceeds to block 106, in whichthe control gate may be formed over the gate dielectric layer. Thecontrol gate may comprise polysilicon or a metal such as TiN, TiAlN, orTaN, and may be deposited using any appropriate method of deposition.The control gate may be separated from the floating gates by the gatedielectric layer. Both the floating gates and the control gate extendinto the recess in the STI region that is defined by the etch stoplayer, and the floating gate may be separated from the substrate by theetch stop layer, thereby improving the gate coupling factor of the NVMdevice. FIG. 15 shows the device 1400 after formation of a control gate1501 to form a NVM device 1500. As shown in FIG. 15, both the controlgate 1501 and the floating gates 1301A and 1302A extend into the recessdefined by etch stop layer 801. The etch stop layer 801 also separatesthe substrate 301 and the floating gates (for example, portion 1502 offloating gate 1301A).

The second embodiment of the process flow of method 100 of FIG. 1, inwhich the etch stop layer may be located only on the sides of the STItrench, is now discussed with respect to FIG. 2B, FIGS. 3-8, and 16-23.First, in block 101 of FIG. 1, STI regions comprising an etch stop layermay be formed in a wafer comprising a silicon substrate. A flowchart ofa method 200B of formation of the STI regions according to the secondembodiment is shown in FIG. 2B. Referring to FIG. 2B, in block 201B,first, a padox layer, which comprises uniform, relatively thin layer ofoxide, may be formed on a top surface of a silicon substrate. FIG. 3shows an embodiment of a device 300 including a silicon substrate 301after formation of a padox layer 302 on the top surface of the siliconsubstrate. Then, returning to FIG. 2B, flow proceeds to block 202B, inwhich a nitride layer may be formed over the padox layer. FIG. 4 showsthe device 300 of FIG. 3 after formation of a nitride 401 over the padoxlayer 302.

Next, returning to method 200B of FIG. 2B, in block 203B the nitride andthe padox may be etched to form a mask for etching of an STI trench. Thepadox acts as an etch stop for the nitride during patterning of thenitride; the padox may then be subsequently patterned. FIG. 5 shows thedevice 400 of FIG. 4 after etching the nitride 401 and the padox layer302. Then, proceeding to block 204B of method 200B of FIG. 2B, the STItrench may be etched in the silicon substrate. FIG. 6 shows the device500 of FIG. 5 after etching of an STI trench 601 in the siliconsubstrate 301. After etching of the STI trench, flow of method 200B ofFIG. 2B proceeds to block 205B, in which an STI liner may be formed inthe STI trenches. The STI liner may comprise oxide, and may be formed byany appropriate method. FIG. 7 shows the device 600 of FIG. 6 afterformation of an STI liner 701 on the bottom and sides of the STI trench601.

Flow of method 200B of FIG. 2B then proceeds to block 206B, in which theetch stop layer may be deposited over the STI liner in the STI trench.The etch stop layer may comprise nitride. FIG. 8 shows an embodiment ofthe device 700 of FIG. 6 after deposition of the etch stop layer 801over the STI liner 701. The etch stop layer covers the bottom and sidesof the STI trench 601. The thickness of the etch stop layer determinesthe distance between the floating gate (discussed below with respect toblock 104) and the substrate; therefore the deposition of the etch stoplayer may be controlled to produce an etch stop layer having a desiredthickness to improve the operation of the finished NVM device. Then, inblock 207B of method 200B of FIG. 2B, a portion of the etch stop layerlocated at the bottom of the STI trench may be removed. Removal of theportion of the etch stop layer located at the bottom of the STI trenchmay be performed using an anisotropic nitride etch or a CH_(x)F_(y)+O₂etch. FIG. 16 shows the device 800 of FIG. 8 after removal of theportion of the etch stop layer 801 located at the bottom of the STItrench 601, exposing the bottom 1601 of the STI trench 601.

Method 200B of FIG. 2B then proceeds to block 208B, in which an STIoxide fill may be deposited over the device, filling STI trench over theetch stop layer. FIG. 17 shows the device 1600 of FIG. 16 afterdeposition of the oxide fill 1701 over the device 1600; the oxide fill1701 fills the STI trench 601 and covers the etch stop layer 801.Lastly, in block 209B of FIG. 2B, the top of the STI oxide fill may bepolished down to expose the top surface of the etch stop layer, theexcess etch stop and nitride on top of the substrate may be removed byetching, the padox may be removed by etching so as to expose the topsurface of the silicon substrate, and the top of oxide fill may befurther removed to the level of the top surface of the siliconsubstrate. The excess oxide fill may be removed by chemical mechanicalpolishing (CMP) in some embodiments. FIG. 18 shows the device 1700 ofFIG. 17 after removal of the excess portion of oxide fill 1701, theexcess portion of the etch stop layer 801, nitride 401, and padox layer302 to expose the top surface of silicon substrate 301. Device 1800 ofFIG. 18 comprises a silicon substrate 301 with STI regions including STIliner 701, etch stop layer 801 over the STI liner 701, and STI oxidefill 1801.

Returning to method 100 of FIG. 1, after formation of STI regionsincluding an etch stop layer on the sides of the STI trench according tothe method 200B outlined in FIG. 2B in block 101 of FIG. 1, flowproceeds to block 102, in which the oxide fill in the STI regions may beetched to form a recess. In the second embodiment of the process flow ofFIG. 1, the oxide fill may be partially etched, such that the etch stoplayer controls the location of the sides of the recess, while a portionof the oxide fill remains at the bottom of the STI trench. The etch ofthe oxide fill may comprise a hydrofluoric (HF) etch in someembodiments. FIG. 19 shows the device 1800 of FIG. 18 after etching theoxide fill 1801 to etch stop layer 801 on the sides of the STI trench toform recess 1902, leaving oxide fill 1901 at the bottom of the STItrench.

Flow of method 100 of FIG. 1 then proceeds to block 103, in which wellimplantation and tunnel oxide growth are performed. The wellimplantation forms active regions in the silicon substrate near the topsurface of the substrate. In some embodiments, the well implantation maybe performed before etching of the STI oxide fill is performed in block102 of FIG. 1. After well implantation, tunnel oxide may be grown overthe implanted well regions of the substrate. The well regionimplantation and the tunnel oxide growth may be performed by anyappropriate method. For example, the tunnel oxide may be grown bychemical vapor deposition (CVD) or in-situ steam generation (ISSG) invarious embodiments. The tunnel oxide may comprise a high k dielectricsuch as HfO₂, HfSiO₂, HfSiON, SiO_(x)N_(y) or Al₂O₃ in some embodiments.In some embodiments, the order of blocks 102 and 103 in method 100 ofFIG. 1 may be reversed, and the etch of the oxide fill that is performedin block 102 may be performed after the well implantation and tunneloxide growth of block 103. FIG. 20 shows the device 1900 of FIG. 19after implantation of well regions 2002 in the silicon substrate 301,and after growth of tunnel oxide 2001 over the well regions 2002.

Turning again to method 100 of FIG. 1, in block 104, the floating gatesare formed by deposition and patterning of a floating gate material,which may be polysilicon or a metal such as TiN, TiAlN, or TaN. Thefloating gates may be deposited by conformal deposition, and formed suchthat a portion of the floating gate located on the etch stop layer inthe STI recess that was formed by removal of the oxide fill from the STIregions. In various embodiments, the sides of the floating gates may bevertical, or in other embodiments the sides of the floating gates may besloped. In embodiments in which the sides of the floating gates aresloped, the etch chemistry of the etch that is used to pattern apolysilicon floating gate may be CH_(x)F_(y)+O₂, and the angle of theslope may be about 10 degrees. In other embodiments, the etch chemistryused to pattern a polysilicon floating gate may be HBr+O or HCl+O.Floating gates with sloped sides may help to prevent formation of voidsduring deposition of the control gate (discussed below with respect toblock 106 and FIG. 23). Additionally, in some embodiments, the sides ofthe floating gate regions may be implanted with dopants afterdeposition. The implantation may comprise tilted implantation in someembodiments. FIGS. 21A-B show the device 2000 of FIG. 20 after formationof floating gates 2101A, 2102A, 2101B, and 2102B. Floating gates 2101Aand 2102A as shown in FIG. 21A have vertical sides extending into recess1902, and floating gates 2101B and 2102 b as shown in FIG. 21B hassloped sides extending into recess 1902. The depth and shape of thefloating gates 2101A, 2102A, 2101B, and 2102B may be dependent on theetch chemistry used to pattern the floating gate material after it isdeposited; a floating gate such as floating gates 2101A, 2102A, 2101B,and 2102B may have any appropriate depth and shape in variousembodiments. Additionally, while FIGS. 22-23, which illustrate furtherprocessing steps of method 100 of FIG. 1, are shown with respect to anexample device 2100A including floating gates 2101A and 2102A withvertical sides, the same processing steps may be applied to the device2100B including floating gates 2101B and 2102B with sloped sides to forma memory device in various embodiments. A NVM that includes floatinggates such as floating gates 2101A-B having sloped sides may help toprevent void formation during deposition of the control gate. Each offloating gates 2101A, 2102A, 2101B, and 2102B comprise a portion thatmay be located in the STI recess 1902 on the etch stop layer 801, whichseparates the floating gates 2101A, 2102A, 2101B, and 2102B from thesubstrate 301, lowering the capacitance between the floating gates2101A, 2102A, 2101B, and 2102B and the substrate 301.

Returning to method 100 of FIG. 1, in block 105, a gate dielectric layermay be deposited over the device, covering the floating gates and theetch stop layer located at the bottom of the recess. The gate dielectriclayer may be formed by conformal deposition, and may include one or morelayers of oxide and/or nitride. The gate dielectric layer may comprise ahigh k dielectric such as HfO₂, HfSiO₂, HfSiON, SiO_(x)N_(y) or Al₂O₃ insome embodiments. Additionally, in some embodiments, the gate dielectriclayer may include an oxide-nitride-oxide (ONO) dielectric layer. FIG. 22shows the device 2100A of FIG. 21A after formation of the gatedielectric layer 2201 over the floating gates 2101A and 2102A andremaining oxide fill 1901 located at the bottom of recess 1902.

Lastly, the flow of method 100 of FIG. 1 proceeds to block 106, in whichthe control gate may be formed over the gate dielectric layer. Thecontrol gate may comprise polysilicon or a metal such as TiN, TiAlN, orTaN, and may be deposited using any appropriate method of deposition.The control gate may be separated from the floating gates by the gatedielectric layer. Both the floating gates and the control gate extendinto the recess in the STI region defined by the etch stop layer and theremaining oxide fill, and the floating gate may be separated from thesubstrate by the etch stop layer, thereby improving the gate couplingfactor of the NVM device. FIG. 23 shows the device 2200 after formationof a control gate 2301 to form a NVM device 2300. As shown in FIG. 23,both the control gate 2301 and the floating gates 2101A and 2102A extendinto the recess defined by etch stop layer 801 and the remaining oxidefill 1901. The etch stop layer 801 also separates the substrate 301 andthe floating gates (for example, portion 2302 of floating gate 2101A).

The technical effects and benefits of exemplary embodiments includeformation of an NVM memory device having an improved gate couplingfactor and therefore improved performance.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an”, and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

1. A method comprising: forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate.
 2. The method of claim 1, wherein forming the STI region comprises: etching a STI trench in the substrate by a second etch, the STI trench comprising a bottom and sides; forming a STI liner on the bottom and sides of the STI trench; forming the etch stop layer over the STI liner; and forming an oxide fill over the etch stop layer.
 3. The method of claim 2, further comprising etching a portion of the etch stop layer located on the bottom of the STI trench by a third etch before forming the oxide fill.
 4. The method of claim 3, wherein the third etch comprises one of an anisotropic nitride etch and a CH_(x)F_(y)+O₂ etch.
 5. The method of claim 2, wherein the first etch comprises etching the oxide fill.
 6. The method of claim 1, wherein the etch stop layer comprises nitride.
 7. The method of claim 1, wherein the floating gate comprises a floating gate material comprising one of polysilicon, titanium nitride (TiN), titanium aluminum nitride (TiAlN), and tantalum nitride (TaN), and wherein forming the floating gate comprises conformal deposition of the floating gate material and etching of the deposited floating gate material by a fourth etch.
 8. The method of claim 7, wherein the floating gate comprises sloped sides having an angle of about 10 degrees, and wherein the fourth etch comprises CH_(x)F_(y)+O₂.
 9. The method of claim 1, wherein the recess in the STI region comprises a bottom and sides comprising the etch stop layer.
 10. The method of claim 1, wherein the recess in the STI region comprises a bottom and sides, wherein the bottom of the recess comprises an oxide fill of the STI region, and wherein the sides of the recess comprise the etch stop layer.
 11. A device, comprising: a substrate; a shallow trench isolation (STI) region located in the substrate, the STI region comprising an etch stop layer, and further comprising a recess in the STI region, the recess having a bottom and sides, wherein the sides of the recess are defined by the etch stop layer; and a floating gate, wherein a portion of the floating gate is located on a side of the recess in the STI region and is separated from the substrate by the etch stop layer.
 12. The device of claim 11, wherein the etch stop layer comprises nitride, and, wherein the floating gate comprises one of polysilicon, titanium nitride (TiN), titanium aluminum nitride (TiAlN), and tantalum nitride (TaN).
 13. The device of claim 11, wherein the etch stop layer is located over a STI liner of the STI region.
 14. The device of claim 11, wherein the bottom of the recess comprises the etch stop layer.
 15. The device of claim 11, wherein the bottom of the recess comprises an oxide fill of the STI region.
 16. The device of claim 11, wherein the floating gate comprises sloped sides, and wherein the sloped sides of the floating gate have an angle of about 10 degrees.
 17. The device of claim 11, further comprising tunnel oxide located directly underneath the floating gate on the substrate, and well regions located in the substrate underneath the tunnel oxide.
 18. The device of claim 11, further comprising: a gate dielectric layer located over the floating gate; and a control gate located over the gate dielectric layer, wherein a portion of the control gate extends into the recess in the STI region.
 19. The device of claim 18, wherein the gate dielectric layer is located directly on a portion of the etch stop layer that is located at the bottom of the recess in the STI region.
 20. The device of claim 18, wherein the gate dielectric layer is located directly on an oxide fill located at the bottom of the recess in the STI region. 